Already have an account? Get multiple benefits of using own account!
Login in your account..!
Remember me
Don't have an account? Create your account in less than a minutes,
Forgot password? how can I recover my password now!
Enter right registered email to receive password!
Configure port A for the lower 4 bits to be inputs and the upper 4 bits to be outputs. The program should chase a logic one from Pa4 -> Pa7, depending upon the condition of Pa0-Pa3 the speed of chase is increased.
Pa0 = 1 Slow Counter Pa1 = 1 Counter Pa2 = 1 Counter Pa3 = 1 Fast Counter If all Pa0, Pa1, Pa2, Pa3 = 0 wait The only major difference is the data direction i.e. this configures 4 input lines Pa0-Pa3 and 4 output lines Pa4-Pa7
Paddr Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 1 1 1 1 0 0 0 0 The full program is shown below
name first padr equ $0000 paddr equ $0001 org $500 ldaa #$f0 staa paddr set up half in and half out loop0 ldaa #$10 staa padr send data jsr delay ldaa #$20 staa padr send data jsr delay ldaa #$40 staa padr send data jsr delay ldaa #$80 staa padr send data jsr delay jmp loop0 delay ldab padr ;get input from port a andb #$0f ;mask of lower nibble only
beq delay ;repeat till selected ldab padr ;get port a data again andb #$8 ; mask off bit 3 pa3 bne loop3 ;if select go to loop3 ldab padr ;get port a data again andb #$4 ; mask off bit 2 pa2 bne loop4 ;if select go to loop4 ldab padr ;get port a data again andb #$2 ; mask off bit 1 pa1 bne loop5 ;if select go to loop5 ldx #$ffff ;assume pa0 is pressed load up x with ffff jmp loop1 ;carry on loop2 ldx #$1 ;load up X with 1 fast jmp loop1 ;carry on loop3 ldx #$f ;load X with f jmp loop1 loop4 ldx #$ff ;load x with ff jmp loop1 loop5 ldx #$fff ;load x with fff slow loop1 ldab #$1f ;nested loop loop6 decb bne loop6 dex bne loop1 ;loop till zero rts ;return back to main end
where should I work?
Measuring and Improving Cache Performance: 1. Reduce the possibility that 2 different memory block will contend for the similar cache location 2. Additional cache levels
T he complexity of adding two matrices of order m*n is mn
Explain the numbering plan for ISDN address structure. The numbering plan for ISDN is evolved with using the following guidelines: 1. This is based on, and is an improvemen
Artificial Intelligence 1. Explain about artificial intelligence? What are the achievements of AI? 2. Elaborate state space search briefly. 3. Prove that A* is optimal.
Q. Define Interrupts in assembly language? An interrupt causes interruption of an ongoing program. A number of the common interrupts are: printer, monitor, keyboard, an error c
reflection in 2d
Given memory partitions of 100k, 500k, 200k, 300k, and 600k (in order), apply first fit and best fit algorithms to place processes with the space requirement of 212k, 417k, 112k an
What is index register? In index mode the effective address of the operand is formed by adding a constant value to the contents of a register. The register used might be either
Computer Architecture Basics: Some of computer architecture at companies such like AMD and Intel uses more fine distinctions: Macro architecture- this is an architectura
Get guaranteed satisfaction & time on delivery in every assignment order you paid with us! We ensure premium quality solution document along with free turntin report!
whatsapp: +91-977-207-8620
Phone: +91-977-207-8620
Email: [email protected]
All rights reserved! Copyrights ©2019-2020 ExpertsMind IT Educational Pvt Ltd