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Register-to-Register Architecture
In this organization results and operands are not accessed straight from main memory by scalar or vector registers. The vectors that are needed currently can be stored in CPU registers. Cray-1 computer accepts this architecture for vector instructions and its CPY comprise 8 vector registers. Every register is able to storing a 64 element vector where one element is of 8 bytes.
Write a CGI program that keeps a list of computers that have contacted the server. If comp1 is contacting first time it will display the message: "This is the first contact fr
Define lazy swapper. Rather than swapping the whole process into main memory, a lazy swapper is used. A lazy swapper never swaps a page into memory unless that page will be re
Determine the importance of computer Hardware Hardware forms the greatest asset of the company, but it reaches obsolescence very quickly. Normally, it is said that every six mo
Q. Input output in assembly program? Software interrupt is a call to an Interrupt servicing program situated in the operating system. Generally the input-output routine in 8086
What is the advantage of dividing an email address into two parts? The division of an e-mail address in two parts is significant since it achieve two objectives. First, the div
Explain the working of a 2-bit digital comparator with the help of Truth Table. Ans. Digital comparator is a combinational circuit which compares two numbers, A and B; and
Yes we can modify the color of sheet tabs. By right clicking on sheet tabs and you will get option change color but you didn't find any option to modify the font of sheet tabs.
Q. Explain Passing Parameters Using Pointers ? This method overcomes the drawback of using variable names directly in procedure. It uses registers to pass procedure pointers to
It speeds execution of distributed applications. It runs on dissimilar platforms. It time independent. No loss for msg delivery i.e. guarantee delivery.
In applications where the required memory capacity cannot be satisfied by a single available memory IC chip, what should the designer do to meet this requirement? Ans: If th
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