Breifly explain memory-to-memory architecture, Computer Engineering

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Memory-to-Memory Architecture

The pipelines can access vector operands intermediate and final results straight in main memory. This necessitates the higher memory bandwidth. Furthermore the information of the offset, base address, vector length must be specified for transferring the data streams between the pipelines and main memory. TI-ASC and STAR-100 computers have accepted this architecture for vector instructions.

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