Basic architecture of digital switching systems, Electrical Engineering

Assignment Help:

Q. Explain the basic architecture of digital switching systems. Explain in detail companding.

Ans:

A simple N X N time division space switch is displayed in Figure. Switch can be represented in an equivalence form as a two-stage network with N X 1 and 1 X N switching matrices for first and second stages corresponding as displayed in Figure. Network has one link interconnecting the two stages. Every inlet/outlet is a single speech circuit corresponding to a subscriber line. Speech is carried as PAManalogue samples or PCM digital samples, occurring at 125-µs intervals. When PAM samples are switched in a time division manner, switching is called analogue time division switching. If PCM binary samples switched, then switching is termed as digital time division switching. In Figure, the interconnected by a suitable control mechanism and speech sample transferred from the inlet to the outlet.

2406_Basic architecture of digital switching systems.png


Related Discussions:- Basic architecture of digital switching systems

Binary division , Binary  Division Similar  to multiplication  divisi...

Binary  Division Similar  to multiplication  division can be seen  multiple  subtractions.  For example  if we have to divide 9 by 4  we can subtract 4 ,2,  times  until is is

Illustrate application specific instruction set processor, Illustrate about...

Illustrate about the term application specific instruction set processor. Application Specific Instruction-Set Processor (ASIP): a. Microcontroller: as Intel, Hitachi, Motor

Explain about subscriber loops signalling, Q. Explain about Subscriber loop...

Q. Explain about Subscriber loops signalling? In a telephone network, subscriber loop signal linger lies upon the kind of a telephone instrument used. The intra exchange signal

Microgrid, how to connect some DG together?

how to connect some DG together?

Digital logical disign, design SR latch with universal logic gates.draw and...

design SR latch with universal logic gates.draw and explain the logic diagrams

Define the binary counting - counters, Define the Binary Counting - Counter...

Define the Binary Counting - Counters? The Binary counter is capable to be constructed from J-K flip-flops by taking the output of one cell to the clock input of the next The J

Signals in noise, Signals in Noise: Let us now consider a weak informat...

Signals in Noise: Let us now consider a weak information signal that is to be amplified by a noisy amplifier. The signal-to-noise ratio (SNR), usually expressed in decibels, be

Common base configuration - bjt, Common base configuration: for pap t...

Common base configuration: for pap transistor connection for common base operation is as follow: common base means base is common to both input and output side of configurati

Write Your Message!

Captcha
Free Assignment Quote

Assured A++ Grade

Get guaranteed satisfaction & time on delivery in every assignment order you paid with us! We ensure premium quality solution document along with free turntin report!

All rights reserved! Copyrights ©2019-2020 ExpertsMind IT Educational Pvt Ltd