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Consider that a list of record or a table is stored in the memory and you wish to find some information in that particular list. E.g. the list comprises three fields as displayed below:
Assume that we want to find the age and ID number of Ravi. If we use conventional RAM, it is essential to give the exact physical address of entry associated to Ravi in the instruction access entry such as:
READ ROW 3
Another alternative idea is that we explore the whole list by means of the Name field as an address in instruction like:
READ NAME = RAVI
Again with serial access memory this option may be implemented simply but it's a very slow process. An associative memory assists at this point and concurrently examines all the entries in the list and returns the desired list very rapidly. SIMD array computers have been developed with associative memory. This memory is content addressable memory by which it's meant that multiple memory words are accessible concurrently. The parallel accessing feature support parallel search and parallel compare too. This ability can be used in numerous applications like:
The inherent parallelism characteristic of this memory has huge advantages and impact in parallel computer architecture. The associative memory is expensive compared to RAM. The array processor built with associative memory is termed as Associative array processor. In this section we explain a number of categories of associative array processor. Kinds of associative processors are based on organisation of associative memory. So first we discuss about associative memory organisation.
What techniques are used to increase the clock rate R? Ans: The 2 techniques used to increase the clock rate R are: 1. We can reduce the amount of processing done in one basi
Write Hit Policies: Write through o Update next level on every write o Cache is always clean o A lots of traffic to next level (mostly write) Write
Q. Explain the odd-even transposition algorithm? The algorithm needs one 'for loop' beginning from I=1 to N it implies that N times and for every value of I, one 'for loop' of
What is a parallel port? A parallel port transfers data in the form a number of bits, typically 8 to 16, concurrently to or from the device.
What are the mapping techniques? a)Direct mapping b) Associative mapping c) Set associative mapping
Address phase: A PCI bus transaction starts having an address phase. The initiator, after seeing that it has GNT# and the bus is inactive, drives the target address onto the
explain different types of parallel processing mechanism
The Standard C Library function is removing. (This is thus one of the few questions in this section for which the answer is not ''It's system-dependent.'') On older, pre-ANSI Unix
Determine about the raster-scan systems Most of the present raster-scan systems contain a separate processor called as display processor. This processor performs graphics func
Q. Perform division in binary showing contents of accumulator, B register and Y register during each step. (Accumulator, B, Y are 5-bit registers) 13 / 2
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