Associative array processing, Computer Engineering

Assignment Help:

Consider that a list of record or a table is stored in the memory and you wish to find some information in that particular list. E.g. the list comprises three fields as displayed below:

331_Associative Array Processing.png

Assume that we want to find the age and ID number of Ravi. If we use conventional RAM, it is essential to give the exact physical address of entry associated to Ravi in the instruction access entry such as:

    READ ROW 3

Another alternative idea is that we explore the whole list by means of the Name field as an address in instruction like:

    READ NAME = RAVI

Again with serial access memory this option may be implemented simply but it's a very slow process. An associative memory assists at this point and concurrently examines all the entries in the list and returns the desired list very rapidly. SIMD array computers have been developed with associative memory. This memory is content addressable memory by which it's meant that multiple memory words are accessible concurrently. The parallel accessing feature support parallel search and parallel compare too. This ability can be used in numerous applications like:

  • Radar signal tracking
  • Image processing
  • Artificial Intelligence
  • Retrieval and Storage of databases that are changing rapidly

The inherent parallelism characteristic of this memory has huge advantages and impact in parallel computer architecture. The associative memory is expensive compared to RAM. The array processor built with associative memory is termed as Associative array processor. In this section we explain a number of categories of associative array processor. Kinds of associative processors are based on organisation of associative memory. So first we discuss about associative memory organisation.


Related Discussions:- Associative array processing

Major task of a computer to carry out instruction execution, The major task...

The major task of a computer is to carry out instruction execution. The key questions that can be asked in this respect are: (a) how are the instructions provided to computer? And

Describe about full adder, Q. Describe about full adder? Let's take ful...

Q. Describe about full adder? Let's take full adder. For this other variable carry from previous bit addition is added let'us call it 'p'. Truth table and K-Map for this is dis

Explain difference between space and time division switching, Through two b...

Through two block diagrams explain the difference between Space division and time division switching. Space and Time Switching: Space Switches: Connections can be made i

What is stack addressing, Q. What is Stack Addressing? In this addressi...

Q. What is Stack Addressing? In this addressing technique operand is implied as top of stack. It isn't explicit however implied. It employs a CPU Register known as Stack Pointe

What is basic time division switching, What is Basic Time Division Switch...

What is Basic Time Division Switching? Basic Time Division Switching: The functional blocks of a memory based time division switching switch is demonstrated in figure and i

What are program-invisible registers, What are program-invisible registers?...

What are program-invisible registers? Ans: the local and global descriptor tables are found in the memory system. To access and specify the address of these tables, program inv

Explain in detail about the random scan display, Explain in detail about th...

Explain in detail about the Random Scan Display   This device using CRT directs the electron beam only to the parts of the screen where a picture is to be drawn. This kind of d

Various interconnection networks-fully connected, Various Interconnection N...

Various Interconnection Networks Fully connected: This is the most controlling interconnection topology.In this each node is directly linked to all other nodes. The shortcomi

Determine the complete or gate and and gate decoder, Q. Determine the comp...

Q. Determine the complete OR gate and AND gate decoder count for an IC memory with 4096 words of 1 bit each, using the Linear select memory organization and Two dimensional Memory

Post interrupts - computer architecture, Post interrupts - computer archite...

Post interrupts - computer architecture: Post interrupts Exact interrupts examine interrupt bit on entering WB Longer latency Handle immediately

Write Your Message!

Captcha
Free Assignment Quote

Assured A++ Grade

Get guaranteed satisfaction & time on delivery in every assignment order you paid with us! We ensure premium quality solution document along with free turntin report!

All rights reserved! Copyrights ©2019-2020 ExpertsMind IT Educational Pvt Ltd