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Consider that a list of record or a table is stored in the memory and you wish to find some information in that particular list. E.g. the list comprises three fields as displayed below:
Assume that we want to find the age and ID number of Ravi. If we use conventional RAM, it is essential to give the exact physical address of entry associated to Ravi in the instruction access entry such as:
READ ROW 3
Another alternative idea is that we explore the whole list by means of the Name field as an address in instruction like:
READ NAME = RAVI
Again with serial access memory this option may be implemented simply but it's a very slow process. An associative memory assists at this point and concurrently examines all the entries in the list and returns the desired list very rapidly. SIMD array computers have been developed with associative memory. This memory is content addressable memory by which it's meant that multiple memory words are accessible concurrently. The parallel accessing feature support parallel search and parallel compare too. This ability can be used in numerous applications like:
The inherent parallelism characteristic of this memory has huge advantages and impact in parallel computer architecture. The associative memory is expensive compared to RAM. The array processor built with associative memory is termed as Associative array processor. In this section we explain a number of categories of associative array processor. Kinds of associative processors are based on organisation of associative memory. So first we discuss about associative memory organisation.
Suppose we have an array-based list A[0..N - 1] and we want to delete all duplicates. LastPosition is initially N - 1, but gets smaller as elements are deleted. Consider the pseudo
What is NULL POINTER Inside main, a FILE * called file. Afterwards, the fopen function, passing it the path to data file, as well as "r", only intending to read from the file.
output devices used in virtual rality
what is the code to detect image forgery using Matlab..??
Q. Simplify Using K-Map 1. M2 + M3 + M5 + M7 + M12 + M13 + M8 + M9 2. M0 + M2 + M4 + M5 + M8 + M10 + M12 3. F(W,X,Y,Z) = ∑ (0,1,2,4,5,6,8,9,12,13,14)
Flynn's Classification This classification was early proposed and studied by Michael Flynn in 1972. Flynn did not believe the machine architecture for organization of parallel
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A full adder logic circuit will have ? Ans. The full adder logic circuit also accounts the carry i/p generated in the earlier stage and it will add two bits. Hence three inputs
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How many AND gates are required to realize Y = CD+EF+G ? Ans. Y = CD + EF + G for realize this two AND gates are needed (for CD and EF).
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