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Q. Addressing Relationship for Main Memory and Cache?
In the normal case there are 2k words in cache memory and 2n words in main memory. The n-bits memory address is splitted in two fields: k bits for index field and (n - k) bits for tag field.
Direct mapping cache organization uses n-bit address to access main memory and k-bit index to access cache. Internal organization of the words in cache memory is as displayed in Figure below. Every word in cache comprises the data word and its associated tag. When a new word is first brought in cache the tag bits are stored alongside data bits. When CPU generates a memory request the index field is used for address to access the cache.
Figure: Addressing Relationship for Main Memory and Cache
The tag field of CPU address is compared with tag in the word read from cache. If two tags match then there is a hit and desired data word is in cache. If there is not any match there is a miss and required word is read from main memory.
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