Write a vhdl testbench to verify your design

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Reference no: EM131081300

Consider an unsigned integer division by constant circuit that accepts an input of 8 bit wide and divides it by constant value 53. The divider circuit should output two values as remainder and quotient As you know the division operator is not synthesizable! As an example of input is 109, the remainder is 3 and quotient is 2 while if input is 23, remainder is 23 and quotient is O.

Design a synthesizable integer division by 53 circuit that performs the above operation. Design your circuit for minimum area. This means that you need to decide what is the minimum proper number of bits needed for each of the intermediate signals and outputs.

Hint: You can use the repeated subtraction method to synthesize this circuit

1. Draw a block diagram of the complete design that implements your algorithm.

2. Write a VHDL code to model this division by constant circuit

3. Write a VHDL testbench to verify your design. Present a test vector that verifies the functionality of the design for all critical cases.

Reference no: EM131081300

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