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1. Assume that a 6 MHz crystal oscillator is connected to OSC_IN and OSC_OUT pins, find a combination of M, N, and R values to generate a PLLCLK output so that fPLLCLK = 80 MHz.
2. Assume that a 15 MHz crystal oscillator is connected to OSC_IN and OSC_OUT pins, find a combination of M, N, and R values to generate a PLLCLK output so that fPLLCLK = 80 MHz.
3. Assume that a 24 MHz crystal oscillator connected to the OSC_IN and OSC_OUT pins is chosen as the clock source of the PLL, what value of M should be chosen for the RCC->PLLCFGR register so that you can select appropriate values for N and Q in the RCC->PLLSAI1CFGR register to generate the Q output at 48 MHz? Wat are your choice for N and Q in the RCC->PLLSAI1CFGR register?
4. Write a sequence of C statements to configure port D pins PD03~PD04 to alternate function AF3 and configure PD08~PD09 pins for alternate function AF6.
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