Reference no: EM13703693

You need to write a verilog model of ring counter.

Question: Write a Verilog model of a positive-edge-triggered 4-bit Ring Counter. Choose one of the two types of ring counter described in the linked Wikipedia article to model: either the Straight Ring (Overbeck) Counter, or the Twisted Ring (Johnson) Counter.

Program: Write a Verilog testbench model that generates a clock signal and tests your chosen ring counter. For the Overbeck Counter, initialize it to '1000' and then run eight clock cycles. For the Johnson Counter, initialize it to '0000' and then run eight clock cycles.

Confirm that your ring counter steps through the eight states shown in the Four-bit ring counter sequences table in the linked Wikipedia article.

The testbench does not need to be self-checking, but your simulation results must show that the ring counter steps though the correct sequence.

Can someone demonstrate me how to write a proper code for this problem and how to complete it. Thanks