Reference no: EM131072037

C4-1. Use an FPGA to implement the following Boolean equation: X AB.

(a)  Create a Block Design File called prob_c4_1.bdf to define the logic circuit.

(b)  Create a Vector Waveform File called prob_c4_1.vwf to test the operation of your design by showing the output waveform for all possible input conditions.

(c)  Build a truth table for the Boolean equation.

(d)  Download the design to the FPGA on your programmer board and demonstrate its operation by monitoring the output LED as you step through all switch combinations shown in your truth table from

part (c).

C4-2. Use an FPGA to implement the following Boolean equation: x = AB +

(a)   Create a Block Design File called prob_c4_2.bdf to defitie the logic circuit.

(b) Create a Vector Waveform File called prob_c4_2.vwf to test the operation of your design by showing the output waveform for all possible input conditions.

(c) Build a truth table for the Boolean equation.

(d) Download the design to the FPGA on your programmer board and demonstrate its operation by monitoring the output LED as you

part (c).

step through all switch combinations shown in your truth table from CX AIM

4-3. Use an FPGA to implement the following Boolean equation:

Section 4-1

4-1. How does programmable logic differ from discrete digital logic lik_e the 7400 series?

4-2. What are two common ways to configure or define logic to PLD pro­gramming software?

4-3. What does HDL stand for in the acronym VHDL?

4-4. List the six steps in the PLD design flow.

4-5. How many different ICs would it take to implement the following equations?

(a)      X = AB + BC

(b)      Y = AB + BC + C + D

4-6. How is pin I identified in the PLCC package style used for the PLD in Figure 4-4?

4-7. What is the purpose of the PLD programmer boards shown in Figure 4-5?

Section 4-2

4-8. How many product terms arc in the following equations?

(a) X = AC + BC + AC

(b) Y = ABC + BC

(c)  z = ABC + ACD + BCD

4-9. How does a PLA differ from a PAL?

4-10. Redraw the PLA circuitry of Figure 4-8 to implement the following SOP equations:

(a)X=AB+AB+AB

(b) Y = AB + AB

4-11. Why is it advantageous to use a CPLD or ASIC that is nonvolatile?

Section 4-3

4-16. What are the two most common methods of design entry for FPGA development software?
4-17. What is the function of the compiler in FPGA development soft¬ware?
4-18. What is the purpose of the three pin stubs in the belf file shown in Figure 4-13(a)?
4-19. VHDL allows the user to enter the logic design via a
editor.

4-20. Define the purpose of the following three VHDL program segments:

(a) Library
(b) Entity
(c) Architecture

4-21. Write the VHDL entity declare for a three-input AND gate. 4-22. Write the VHDL architecture for a three .input AND gate.

4-23. Draw the logic circuit to be implemented by the following VHDL architecture body: