Individual logic gates

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Reference no: EM131069378

Instructions:

Please download this document and type in your answers for questions in parts 1 and 2; save this document using the following format:  CE212Lab5firstname_lastname.doc.

Introduction

Individual logic gates are limited in what they can do. However, circuits that consist of multiple gates can make decisions, work through mathematical computations, control other circuits, and perform many other complexoperations. Even the most advanced and complicated microprocessors consist of many interconnected basicgates. Combinational logic circuits are circuits that combine logic gates so that the state of the inputs alonedetermines the state of the output. The binary-to-octal and binary-to-hexadecimal convertersare examples of combinational logic circuits. The value on the output display depended only upon the state ofthe input switches.

In Part 1 of this experiment, you will examine how to design and implement a 2-of-3 voting circuit by 1)

defining the relationship between the input and output states with a truth table, 2) translating the truth tableentries into a Boolean expression, and 3) verifying the circuit implementation for the Boolean expression bysimulating the circuit in Multisim. In Part 2, you will examine how to simplify combinational logic usingBoolean algebra and graphical tools called a Karnaugh map and verify the simplified expression for the 2-of-3voting circuit.

Reading       

Kleitz, Digital Electronics:  A Practical Approach with VHDL, 9th Edition, Chapter 5

Multisim Files

Part 1: Digital_Exp_05_Part_01

Part 2: Digital_Exp_05_Part_02

Key Objectives

Part 1: Analyze, define, and verify the logic for a 2-of-3 voting circuit.

Part 2: Use Boolean algebra and Karnaugh map techniques to simplify the logic for the 2-of-3 voting circuit.

Part 1:  The 2-of-3 Voting Circuit

A panel of three judges for the Digital Idol circuit design competition needs a circuit that will indicate whethera digital circuit project will progress to the next level of the competition. A project will advance to the nextlevel if at least two of the judges approve the project with a "Yes" vote. A project will not advance if at leasttwo of the judges reject the project with a "No" vote.

5.3 Defining the Logic Function

Complete the truth table in Table 5-1 by indicating whether or not each combination of "No" and "Yes" votes cast by the three judges (called A, B, and C) will approve the project so that it advances to the next level of competition.

Table 5-1:  Truth Table for Voting Logic (0="No", 1="Yes)

JUDGE

PROJECT

APPROVED

JUDGE

PROJECT

APPROVED

A

B

C

A

B

C

0

0

0

0

1

0

0

 

0

0

1

0

1

0

1

 

0

1

0

0

1

1

0

 

0

1

1

1

1

1

1

 

5.4 Translating the Truth Table

Translating the truth table into a Boolean expression consists of ANDing the input terms for each truth tableentry for which the output is "1", and then ORing these product terms together to create a sum-of-product (SOP) expression for the logic function. If the input term for an entry is a "1" use the true (noninverted) form of the input. If the input term for an entry is a "0", use the complement (inverted) form.

Example: What AND term corresponds to A = 0, B = 1, and C = 1?

The A variable is "0" so the complement A' is used. The B variable is "1" so the true form B is used. The C variable is "1", so the true form C is used. The corresponding AND term is A'BC.

Use the data in Table 5-1 to write the SOP expression for 2-of-3 voting logic function.

A'BC + AB'C + ABC' + ABC

5.5Verifying the 2-of-3 Voting Logic

1) Open the Multisim file Digital_Exp_05_Part_01.

2) For each combination of votes in Table 5-2,

a. Use the "A", "B", and "C" keys to set the vote for each judge. Alternatively, you can click on each switch to open or close it.

b. Record the result of the vote Table 5-2.

3) Compare the results of Table 5-2 with the results of Table 5-1. Do the table results match?

Table 5-2:  Results of Voting Logic Circuit

SWITCH SETTINGS

(Closed=0, Open=1)

OUTPUT

STATE

(OFF=0,

On=1)

SWITCH SETTINGS

(Closed=0, Open=1)

OUTPUT

STATE

(OFF=0, ON=1)

A

B

C

A

B

C

0

0

0

 

1

0

0

 

0

0

1

 

1

0

1

 

0

1

0

 

1

1

0

 

0

1

1

 

1

1

1

 

Questions for Part 1

1) Why does the Multisim circuit Digital_Exp_05_Part_01 use three cascaded OR gates to OR the AND

terms together?

2) Suppose you wish to modify the circuit in Digital_Exp_05_Part_01 so that the output indicates that a

project is rejected rather than approved. How could you do this?

Part 2: Logic Simplification

5.6 Boolean Algebra

The laws and rules of Boolean algebra shown in Table 5-3 can be used to simplify logic expressions so that circuits require fewer gates with fewer inputs. This reduces circuit complexity and the costs of parts and manufacturing. Advantages of Boolean algebra are that it rigorously proves that two logic expressions are equivalent and it can be used to reduce expressions with (in theory) any number of variables and terms. A disadvantage is that Boolean algebra does not guarantee that an expression is the minimum SOP expression or even that you will find the minimum SOP expression. Another disadvantage is that there is no "standard procedure" on how to proceed, so that some ingenuity is often required in simplifying an expression and more than one process can arrive at the same result.

1) Begin with the Boolean expression in the first row of Table 5-4.

2) Indicate the Boolean rule or law in Table 5-3 that is applied to derive the new expression for each row

of Table 5-4 (the first two simplifications are done for you)

3) Continue through the table, indicating the Boolean rule or law that is applied at each step to simplify

the 2-of-3 voting logic to its minimum SOP form.

What does the final logic expression indicate?

5.7 Karnaugh Map

The Karnaugh map is a structured way to simplify a Boolean expression. Its main advantage is that it can

always reduce an expression to its simplest SOP form. Its major drawback is that it is limited to simplifyingexpressions with five or fewer input variables.

1) Use the data from Table 5-1 to fill each cell of the blank Karnaugh map in Figure 5-1 with the output

corresponding to the combination of input variables represented by that cell.

2) Group the cells containing a "1" according to the following rules:

a. Each cell containing a "1" must be included in at least one group. Cells may, but need not be,

included in more than one group.

b. Cells in each group must be horizontally or vertically adjacent to each other (i.e., no diagonal

groups). Karnaugh maps "wrap around" so that the top and bottom rows are vertically adjacent toeach other and the leftmost and rightmost columns are horizontally adjacent to each other.

c. Groups must be essentially rectangular in form, so that every row in a group includes the samenumber of columns, and every column in a group includes the same number of rows.

d. The number of cells in each group must be a power of 2, so that each group contains 1 cell, 2 cells,4 cells, etc.

                e. Each group must contain as many cells as possible.

3) Each group corresponds to an AND term in the final simplified expression. To determine the variables

AND term, write down the input variables that are common to each cell in the group.

AND Term 1: AB

AND Term 2: BC

AND Term 3: AC

4) OR the AND terms together to derive the final expression.

Final expression: AB + BC + AC

5.8 Verification of Simplified Logic

1) Open the Multisim file Digital_Exp_05_Part_02.

2) For each combination of votes,

a. Use the "A", "B", and "C" keys to set the vote for each judge. Alternatively, you can click on each

switch to open or close it.

b. Record the result of the vote Table 5-5.

3) Compare the results of Table 5-5 with the results of Table 5-2. Do the table results match?

SWITCH SETTINGS

(Closed="0", Open="1"_)

OUTPUT

STATE

(OFF=0,

ON=1)

SWITCH SETTINGS

(Closed="0", Open="1")

OUTPUT

STATE

(OFF=0,

ON=1)

A

B

C

A

B

C

0

0

0

 

1

0

0

 

0

0

1

 

1

0

1

 

0

1

0

 

1

1

0

 

0

1

1

 

1

1

1

 

Questions for Part 2

1) How does simulating the Multisim circuit Digital_Exp_05_Part_02 verify that the simplified logic

expression is functionally equivalent to the original expression?

2) If you wished to ensure that a three-variable Boolean expression was in its minimum SOP form, which of the two simplification methods would you use? Why?

3) Is the Karnaugh map group shown in Figure 5-2 a valid group? Why or why not?

Reference no: EM131069378

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