Reference no: EM131226555

The design of the processor is also included. language for the processor is in system verilog

- In this assignment you will design the instruction set architecture of a simple microprocessor.

- Assignemt 2 is a group assignment. Each group should consist of two students.

You are welcome to form your own group. It is fine if you prefer to work alone.

- This assignment is due on the Friday of week-9, at 17:00 hrs. Please submit your report via blackboard. Go to the ‘Assessments' folder and then follow the ‘Assignment 2.1 submission portal' link.

In addition, each group is required to submit the hardcopy of the report which should include the following:

- The assessment item cover sheet;

- Description of your design.

The report should be dropped in the ELEC3720 drop-box located in the ground floor of the EA building before the deadline.

- The project report must at least clearly describe the instruction set architecture, and how that architecture is implemented on hardware.

- You will be asked to demonstrate the hardware implementation of your design in Assignments
2.2 and 2.3.

- Note that you are may be required to answer some questions on your design some time during the scheduled lab hours on week 10.Problem.

1. Design the instruction set architecture of a single cycle processor with 18 bit wide instructions, and data-word width of your choice. Show the hardware implementation details of the processor.

In particular, provide the
- Instruction set along with the binary codes
- Instruction encoding/decoding logic
- Discuss various tradeoffs made in your design to optimize the following:
- Instruction coverage
- Dataword width,
- Number of registers,
- Memory adressing scheme (byte or word addressable, base/offset based addressing)
- Memory address and offset range
- Jump offset range
- Branch offset range

- Show the data path needed to implement your design
- Discuss the the control signals and their logic

Notes.
The complexity and the effort needed depends significantly on the data word width of the processor. This the marks automatically depend on the data word width. You should aim for at least 16 bit wide data words.

The utility and efficiency of a processor depends significantly on the number of registers. Hence one prefers to have as many resgisters as possible. However, having more than 32 registers typically slows down a processor due to the increase in the address decoding time.

Similarly, it is desirable to have large memory offset range, jump offset range and branch offset range.

Aim to implement as many instructions from the standard MIPS instruction set as possible, and justify why it is not required/possible to implement more.

Marking criterion.
The mark is allocated as follows:

1. Description of the instruction set

2. Instruction encoding/decoding logic

3. Rationale behind the design and associated design trade-offs

4. Instruction coverage
- ALU instructions with register operands
- Multiplication/Division instructions with register operands
- Shift instructions with register operands
- ALU instructions involving constant operands
- Branch instructions
- Jump instructions
- Memory read and write instructions

5. Description of datapath, control signals and control signals' logic

Note: The marks in points 2, 4 and 5 will depend on the simplicity of the hardware implementation needed to support the designed instruction set. If the hardware needed involves circuits with large delay, then the processor throughput decreases. That is considered as a serious demerit.

Attachment:- 8.pdf