Reference no: EM133139478
Question: In this project you will implement a finite state machine and a circuit that allows a user to enter a list of numbers into a register file, and then press a button to determine if the list is sorted in increasing order. This circuit for this project will have two modes that are described below.
Initialization Mode: During this stage the numbers are loaded one by one into the register file. Two values will be provided by the user through the switches on the Alterra board: the address and the number. The address specifies in which register the number should be stored. A LOAD button or switch is used to load each value into the register file. Once all the numbers are loaded into the register file, a different switch is used to change modes. (Note that the loading may be out of order.)
Checking Mode: A VAUDATE button or switch needs to be pressed to begin the validation process. The machine should iterate through the registers and compare each with its neighbor in the address space. If the contents of the two registers are not sorted in increasing order, then the machine should stop the iteration and indicate with the LEDs or in some other way the position of the exception. That is, the address or location of the first register that has a lower value than the preceding register.
Your circuit must have a register file with eight 4-bit registers. The values stored in the registers must be visualized on the eight 7-segment displays. The rest of the datapath should contain the comparator circuit that is used for checking and any other components that may be necessary.
RUBRIC
Each of the following steps must be in its own design file. Demonstrate each step individually to receive credit.
a. Design and demonstrate a register file with one write port and two read ports. Show that you can write and read from the register file, induding reading from two registers during the same clock cycle.
b. Design and demonstrate the comparator circuit.
c. Design and demonstrate one of the modes of the finite state machine.
d. Put together all of the individual components from Parts a, b, and c and demonstrate that the complete task with both modes can be performed.
e. Submit a written final report.
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