How you are going to control the loading of this register

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Reference no: EM132121138

Register design A CPU register is simply a row of flip-flops (i.e. SR, JK, T, etc) put side by side in an array to make the size of register required.

For example, an 8 bit register has 8 flip-flops side by side for storage of bits.

The same would be true for 16 or 32 or 64 bit registers except there would be 32 or 64 flip flops. You are to design (using gates) a 4 bit register.

Show four inputs labeled IN0, IN1, IN2, IN3 (IN0 is the 1sb) and four outputs labeled OUT0, OUT1, OUT2, OUT3 (OUT0 is the 1sb).

Show how you are going to control the loading of this register. A single control wire labeled ("LOAD REG") should be used. The outputs may be present all the time.

Do this in some nice looking drawing package using gate level design, i.e. show the gates! Logic diagrams, NOT wiring diagrams.

I would suggest that you use ALTERA's Quartus-II software from CpE-272. (The lab handout from 272 will be in the e-Campus attachments.) [You could use another logic drawing tool or you can make your own using the program "dia" and its tools. You would probably be ahead to leam Quartus-II better... .rsn]

The link to download the quartus| ll software is available here. It requires you to create an account with them, but otherwise it's completely free.

We are actually using the "web edition" in the lab also, which is the free edition. There is a Linux version and a Windows version but no Mac Version.

Reference no: EM132121138

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