How many word-line address bits can be accommodated

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For a particular DRAM design, the cell capacitance CS =35 fF and VDD =1.2 V. Each cell represents a capacitive load on the bit line of 0.8 fF. Assume a 20-fF capacitance for the sense amplifier and other circuitry attached to the bit line. What is the maximum number of cells that can be attached to a bit line while ensuring a minimum bit-line signal of 25 mV? How many bits of row addressing can be used? If the sense-amplifier gain is increased by a factor of 4, how many word-line address bits can be accommodated?

Reference no: EM131021331

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