How many states are required for this fsm

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An n-state FSM is to have only a clock input and a single output D whose value is 1 if and only if the number of active clock edges is a multiple of 5. The FSM is to be implemented using only a single r-bit register and a 2" x w-bit ROM. What are the minimal ROM dimensions k and W? How many states are required for this FSM?

Reference no: EM131322933

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