How many cycles in an ldr data hazard stall

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Reference no: EM133218786

Question: Round answers to two decimal places. We have seen that each LDR that triggers a data hazard forces a one-cycle stall in a standard 5-stage pipelined ARM processor. If the ALU is pipelined into two halves:

1. How many cycles in an LDR data hazard stall?

2. Can forwarding avoid needing any non-LDR, non-branch stalls? {Y or N}

3. With 2 ALU pipeline stages and 30% data hazards, 1/3 of which are LDR data hazards, what is the average CPI?

Reference no: EM133218786

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