Estimating the average memory access time

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Reference no: EM1320737

Suppose that it takes 1 cycle to access and return the information on the data-TLB hit and 1 cycle to access and return the information on the data-cache hit. A data-TLB miss takes 300 cycles in order to resolve, and a data-cache miss takes 100 cycles to resolve. The data-TLB hit rate is 0.99, and the data-cache hit rate is 0.95. Explain the average memory access time for the load data reference? Now data cache is an L1 D-cache and is backed up by an L2 uni?ed cache. Every data reference which misses in L1 has the 60% chance of hitting in L2. A miss in L1 followed by the hit in L2 has a latency of 10 cycles. Explain the average memory access time for the load data reference within this new con?guration?

Reference no: EM1320737

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