Draw the logic diagram of a four-bit register

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1. Draw the logic diagram of a four-bit register with clocked JK FFs having control inputs for the increment, complement, and parallel transfer micro-operations. Show how the 2's complement operation can be realized using this register.

2. Design a two-bit counter that counts up when control variable C is a 1 and counts down when C is a 0. No counting occurs when the control variable D is a 0.

Reference no: EM131393182

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