Design two state diagrams each for mealy and moore machines

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Reference no: EM131620559

Assignment

1. Solve the following problems:

a. Simplify the following Boolean function using algebraic manipulation:

X'YZ + X'YZ' + XZ

b. Prove the identity of the following Boolean function using algebraic manipulation:

A'B'C'D' + A'B'CD'+ AB'C'D' + AB'CD' = B'D'

c. Simplify the given expression to its Sum of Products (SOP) form using Boolean postulates. Draw the logic circuit for the simplified SOP function

Y = (A + B) (A + (AB)') C + A' (B + C' ) + AB+ ABC

d. Minimize the logic function Y (A,B, C, D) =

∑ (0,1,2,3,5,7,8,9,11,14) by using Karnaugh Map. Draw logic circuit for the simplified function.

2. Draw the state diagram for the Table 1 below that describes a finite-state machine which has one input x and one output z

Present State	Next State		Output (z)
Present State	x = 0	x = 1	x = 0	x = 1
A	A	E	1	0
B	C	F	0	0
C	B	H	0	1
D	E	F	0	0
E	D	A	0	1
F	B	F	1	1
G	D	H	0	1
H	H	G	1	0

Table 1

3. Design two State Diagrams, each for Mealy and Moore machines, for a sequence detector that outputs a 1 when it detects the final bit in the serial data stream, "1101."

4. Consider the following state diagram in Figure 1 for a synchronous circuit with one input X and one output Z. Analyze this state diagram and draw its circuit implementation using JK flip-flop (state Q0) and T Flip-flop (state Q1) and MUX-4x1 for Z

1603_State Diagram.jpg
Figure 1

5. Consider the following clocked sequential circuit in Figure 2, with one input (X) and one output (Z):

444_Clocked Sequential Circuit.jpg
Figure 2

a. Drive a state table and draw a state diagram for the circuit 8 Marks

b. Redesign this circuit by replacing the Q₁ flip-flop (i.e. the D flip-flop holding Q₁ state) with a JK flip-flop, and the Q₂ flip-flop with a T flip-flop. Only show the excitation equations (or state equations) for J₁, K₁, and T₂.

c. Use MULTISIM to verify the function of the designed circuit in Part (b)

6. Write a Behavioral VHDL description for a 4-bit shift register. The shift register is to be negative edge triggered. Sin is a serial input to the most significant bit of the shift register. Sout is a serial output from the least significant bit of the shift register. En_n is an active low enable. sreg is the 4-bit register. Write only the VHDL ENTITY and ARCHITECTURE construct.

Reference no: EM131620559

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