Cycle miss penalty for reaching main memory

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Reference no: EM131291619

1. Assume a multi-level cache. The L1 cache has a miss-rate of 8%. There is miss penalty of 12 cycles for reachingthe L2 cache. The L2 cache has a miss-rate of 5%. There is a 100 cycle miss penalty for reaching main memory.What is the average miss penalty for this cache?

2. You have an L1 cache with a write through, non-write allocate policy, and an L2 cache with a write back, write allocate policy. What will happen on a write miss in the L1 cache? Consider both the case of the block being in L2,and having to go to main memory to fetch the block.

3. Assume a cache with a write-through policy, non-write allocate. Your cache has a miss rate of 5%. There is a150 cycle miss penalty. Additionally, it takes an extra 30 cycles to do a write. Your program has a base CPI of 1, is20% loads, and 5% stores. What will its CPI be?

Reference no: EM131291619

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