Reference no: EM131416861

Assignment: VHDL Design, Muxes, and Decoders Name:

Designing with VHDL

Please show your work and for each problem, list all references used or students consulted

1. (Adapted from Problem 6 of Digilent Real Digital Exercise 4)

Five judges are scoring a particular event, and they need a device to help them decide how well the event is received. Each judge has a single switch that they can use to enter a "like" or "dislike" vote (assume a switch outputs a ‘1' for "like").

a) Find the Boolean expression for a circuit that can indicate a "majority like" of 3 or more "good" votes. This Boolean expression does not need to be minimized. You can assume the judges' inputs are A, B, C, D, and E.

b) Use VHDL to define this circuit:

2. Complete the truth table and circuit sketch for a 4-to-1 mux.

S1	S0	Y

3. Use a VHDL when or with-select statement to implement the 4-to-1 mux from question 2. Assume a 4-bit bus "I" and a 2-bit bus "S" are used as the inputs and "Y" is the output signal.

4. Suppose an enable input is added to the 4-to-1 mux from question 2. The enable input operates in the following manner: if enable = ‘1', then the mux will operate normally, otherwise, if enable = ‘0', then the output Y will be ‘0'. How must you change the schematic in order to correctly add and implement this enable signal? Please explain.

5. Complete the truth table and circuit sketch for a 3-to-8 decoder.

S2	S1	S0	Y7	Y6	Y5	Y4	Y3	Y2	Y1	Y0

6. Use a VHDL when or with-select statement to implement the 3-to-8 decoder from question 5. Assume a 3-bit bus "S" is used as the input and an 8-bit bus "Y" is used as the output.

7. Suppose an enable input is added to the 3-to-8 decoder from question 5. The enable input operates in the following manner: if enable = ‘1', then the decoder will operate normally, otherwise, if enable = ‘0', then all outputs Y0-Y7 will be ‘0'. How must you change the schematic in order to correctly add and implement this enable signal? Please explain.