Write hit policies, Computer Engineering

Write Hit Policies:

  • Write through

o   Update next level on every write

o   Cache is always clean

o   A lots of traffic to next level (mostly write)

  • Write back

o   Write to cache and mark block dirty

o   Update primary memory to eviction

o   Less traffic to next ,but more complicated eviction and coherence

  • Reservation problem

o   Reads use directly and data array at the same time

o   Write use directory first then data array

o   How to we pipeline to permit one read or write per cycle?    

 

Posted Date: 10/13/2012 5:27:29 AM | Location : United States







Related Discussions:- Write hit policies, Assignment Help, Ask Question on Write hit policies, Get Answer, Expert's Help, Write hit policies Discussions

Write discussion on Write hit policies
Your posts are moderated
Related Questions
Q. Define the Register Addressing mode? When operands are taken from registers implicitly or explicitly it is known as register addressing. These operands are termed as regis

SQL Injection includes entering SQL code into web forms, eg. login fields, or into the browser address field, to access and manipulate the database across the site, application or

Types of reasoning - First-order logic: Atleast five types of reasoning can be acknowledged here. • Firstly, why and how do we will think for the killer usually left a silk

The objective of this practical assignment is to use the POSIX environment to write a program that simulates the supply and demand between three processes: warehouse, factory and r

Name two special purpose registers. Index register Stack pointer

Normal 0 false false false EN-US X-NONE X-NONE

What is layer? A layered system is ordered set of virtual worlds. Every build-in terms of one's below it and providing the execution basis for one above it. The objects in ever

Q. Illustration of cache size of a system? Cache Size: Cache memory is very costly as compared to main memory and therefore its size is generally kept very small.  It has bee

Define Edge Triggered D flip-flop? D latch has only two inputs C(control) and D(data). The operation of a D flip-flop is a lot simpler and it has only one input addition to the

What is the function of a TLB (translation look-aside buffer)? A small cache called the TLB is interporated into MMU, which having of the page table entries that correspondi