What do you mean by instruction pipelining, Computer Engineering

After considering instruction execution let's now describe a concept which is very popular in any CPU implementation. This conception is instruction pipeline. 

To extract better performance as said earlier instruction execution can be done through instruction pipeline. The instruction pipelining includes decomposing of an instruction execution to some pipeline stages. Some of the common pipeline phases can be instruction fetch (IF), instruction decode (ID), operand fetch (OF), execute (EX), store results (SR).  An instruction pipe caninclude any combination of such stages. A main design decision here is that instruction stages must be of equal execution time.

A pipeline allows overlapped execution of instructions. So during the course of execution of an instruction, following can be a scenario of execution.

2046_What do you mean by INSTRUCTION PIPELINING.png

                                                    Figure: Instruction Pipeline                            

Please note following observations about above figure:

  • Pipeline stages are just like steps. So a step of the pipeline is to be complete in a time slot. Size of the time slot will be administered by the stage taking maximum time. So if the time taken in different stages is almost similar we get the best results.
  • First instruction execution is completed on completion of 5th time slot thoughsubsequently in every time slot the next instruction gets executed. Thus in ideal conditions one instruction is executed in pipeline in each time slot.
  • Please note that after 5th time slot and afterwards the pipe is full. In the 5th time slot the phases of execution of five instructions are:

SR (instruction 1) (Requires memory reference),

EX (instruction 2) (No memory reference),

OF (instruction 3) (Requires memory reference),

ID (instruction 4) (No memory reference),

IF (instruction 5) (Requires memory reference),

The Pipelining Problems:

  • On the 5th time slot and afterwards there can be a memory or register conflict in the instructions which are performing memory and register references that is various phases may refer to same memory/registers location. This will yield in slower execution instruction pipeline which is one of the higher number instruction has to wait till lower number instructions completed effectively pushing whole pipelining by one time slot.
  • Another significant situation in Instruction Pipeline can be the branch instruction. Presume that instruction 2 is a conditional branch instruction then by the time the decision to take branch is taken (at time interval 5) three more instructions have already been fetched. So if the branch is to be taken then whole pipeline is to be emptied first. So in such cases pipeline can't run at full load.

 

Posted Date: 7/27/2013 3:12:09 AM | Location : United States







Related Discussions:- What do you mean by instruction pipelining, Assignment Help, Ask Question on What do you mean by instruction pipelining, Get Answer, Expert's Help, What do you mean by instruction pipelining Discussions

Write discussion on What do you mean by instruction pipelining
Your posts are moderated
Related Questions
i want to make an assignment about kirchoff''s law

Sir/Mam, I want to know the application of Theory of computation in DBMS

The conflict between too hot and too cold or too slow and too fast can be resolved using don't care states. Don't care states are used when i) the state of the output is not

Write the importance of operating system. Describe the working methodology of online and real-time operating system with the help of two examples of each.

What are the measures or precautions to be taken in the Design when the chip has both analog and digital portions? As today's IC has analog components also inbuilt, some design

Q. Uneven Load Distribution in parallel computers? In parallel computers the problem is split in sub-problems in addition is assigned for computation to several processors howe

Question Use the National Geophysical Data Center software tool to find the magnetic declination. The link to the web site is in Useful Links on the course Blackboard home page

Briefly explain how the server control validation controls work? A validation control works by evaluating the value of an input server control on the page to see whether it me

Define dynamic loading. To get better memory-space utilization dynamic loading is used. With dynamic loading, a routine is not loaded unless it is called. All routines are kept

A model for parallel programming is an abstraction in addition its machine architecture is independent. A model is able to be implemented on different hardware and memory architect