War (write after read) - data hazards , Computer Engineering

WAR (write after read) - Data hazards in computer architecture:

WAR (write after read) - j tries to write at destination before it is read by i , hence i  wrongly gets the new value. This cannot happen in our instance pipeline because all reads are near the beginning (in ID) and all writes are late (in WB). This hazard take place when there are some instructions that write results early on in the instruction pipeline, and other instructions that read a source late on in the pipeline.

Because of the normal structure of a pipeline, which naturally reads values before it writes results, such type of hazards are rare. Pipelines for difficult instruction sets that hold up auto increment addressing and need operands to be read lately in the pipeline could build a WAR hazards.

If we customized the DLX pipeline as in the above instance and also read some operands late, such as the source value for a store instruction, a WAR hazard could be take place. Here is the pipeline timing for such type of potential hazard, highlighting    the stage where the     clash    takes place:

1579_WAR (write after read) - Data hazards.png

If the SW reads R2 at the  time of second half of its MEM2 stage and the Add writes R2 during the first half of its WB stage, the SW will wrongly read and store the value genrated by the ADD instruction.

Posted Date: 10/13/2012 4:13:23 AM | Location : United States







Related Discussions:- War (write after read) - data hazards , Assignment Help, Ask Question on War (write after read) - data hazards , Get Answer, Expert's Help, War (write after read) - data hazards Discussions

Write discussion on War (write after read) - data hazards
Your posts are moderated
Related Questions
Hardware Support for paging

The Standard C Library function is removing. (This is thus one of the few questions in this section for which the answer is not ''It's system-dependent.'') On older, pre-ANSI Unix

Q. Show the developments that happened in third generation? The main developments that happened in third generation can be summarized as below: Application of IC circuit

Q. Define the ADDRESSING MODES? The elementary set of operands in 8086 can reside in memory, register and immediate operand. How can these operands be retrievedby various addre

Efficiency of Vector Processing over Scalar Processing: We know that, a sequential computer processes scalar operands one at a time. Thus, if we have to process a vector of len

Greedy Search - artificial intelligence: If we have a heuristic function for states, defined as above, so we can simply measure each state with respect to this measure and ord

Explain the architecture of SS7 . A block schematic diagram of the CCITT no. 7 signaling system is demonstrated in figure. Signal messages are passed by the central proces

Describe about the Layered computer design Introduction Layered computer design focuses on computer design. It uses top-down, layered approach to design and also to improve

i want program code for the above question in c language

Eliminating data hazards: Forwarding NOTE: In the following instance, computed values are in bold, whereas Register numbers are not. Forwarding involves adding output