Suppose a logical address space is 1KB, and the page-size is 16 bytes. Assume no page is in the main memory for this process initially and the pure demand paging is used. Current free frame list is {2,5,8,1,...}.  The first frame in the free frame list will be used whenever needed. Suppose TLB has two entries. Both TLB and page table are empty initially. FIFO is used as TLB replacement algorithm. Suppose the following logical address is accessed in order: 0x3d,0x30,0xe5,0x7d, 0x33, 0xef. For each of the following address access:

1. specify the physical address that is mapped to it.

2. Suppose it takes 10 ns to access TLB, and 100ns to access memory, and 8ms to handle page fault. How long time it takes to access this address?

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