Using your cache simulator and using smalltex.din as your memory trace determine the total miss rate, compulsory miss rate, capacity miss rate, and conflict miss rate for the following cache configurations by varying the inputs as suggested below. Examine your results/observations in each case and compare them to a run using dineroiv (a commercial cache simulator). This exercise is to validate the operation of your simulator compared to a commercial simulator and to familiarize yourself with the results that occur for each architecture. Comparing your results with dinero validates your cache simulator. Answering the questions below will help you gain a deeper understanding of the function/operation of caches with respect to various trace files and any patterns within trace files.
1. Keeping block size constant (say 64 bytes) compare the different replacement policy's with several cache sizes (say 16, 64, 256, 512KB) and associativity (direct, 2-, 4-, 8-way, fully associative). Note the trends and confirm your observations from your cache simulator with dineroiv
2. Keeping replacement policy constant (for random and then LRU) and block size constant (say 64 bytes) collect total, compulsory, capacity, and conflict miss rates for each of the following cache organizations and compare with the results from dineroiv.:-
3. Cache sizes 4, 16, 64, 128, 256, 512 KB,
4. Degree of associativity 1-way, 2-way, 4-way, 8-way, fully.
5. To ensure that your cache simulator is fully operational you should be able to perform the following:-
a. Accept any block sizes from 2 bytes to 2048 bytes,
b. Accept any cache size from 1Kb to 8MB,
c. Accept either LRU or random replacement policy for each run,
d. Accept the following degree of associativity, Direct, 2-way, 4-way, 8-way, and fully associative.
6. Additionally, to help you anaylze the operation of caches with a trace file be prepared to perform the following:-
(a) What is the largest address in smalltex.din? (Write a small C program to find this value is it will affect your declarations <=> int, long long, unsigned,...etc.)
(b) Is there a pattern in the trace file - if so, estimate the occurrences of the pattern and how it will impact (validity, fair test, etc) on the performance of a cache simulator. (Hint. Again a small C program that can find a given address and outputs the line number for each occurrence)