Registers - processor, Computer Engineering

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These will be independent of each other and will not affect to each other, and so they can be fed into two different implementations units and run in parallel. The ability to remove instruction level parallelism (ILP) from the instruction stream is necessary for good performance in a modern CPU.

Predicting which code can and cannot be divide up this way is a very difficult task. In many cases the inputs to one line are dependent on the output from a different, but only if some other condition is true. For instance, take the slight modification of the example noted before, A = B + C; IF A==5 THEN D = F + G. In this case the calculations stay independent of the other, but the second command needs the results from the first calculation in order to know if it should be run at all.

In these cases the circuitry on the CPU typically "guesses" what the condition will be. In something like 90% of all cases, an IF will be taken, suggesting that in our example the second half of the command can be safely fed into another core. Though, getting the guess wrong can cause a significant performance hit when the result has to be thrown out and the CPU waits for the results of the "right" command to be calculated. Much of the improving performance of modern CPUs is due to enhanced prediction logic, but lately the improvements have started to slow. Branch prediction accuracy has arrived at figures in excess of 98% in recent Intel architectures, and enhancing this figure can only be achieved by devoting more CPU die space to the branch predictor, a self-defeating tactic because it would make the CPU more expensive to manufacture.


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