Registers - processor, Computer Engineering

These will be independent of each other and will not affect to each other, and so they can be fed into two different implementations units and run in parallel. The ability to remove instruction level parallelism (ILP) from the instruction stream is necessary for good performance in a modern CPU.

Predicting which code can and cannot be divide up this way is a very difficult task. In many cases the inputs to one line are dependent on the output from a different, but only if some other condition is true. For instance, take the slight modification of the example noted before, A = B + C; IF A==5 THEN D = F + G. In this case the calculations stay independent of the other, but the second command needs the results from the first calculation in order to know if it should be run at all.

In these cases the circuitry on the CPU typically "guesses" what the condition will be. In something like 90% of all cases, an IF will be taken, suggesting that in our example the second half of the command can be safely fed into another core. Though, getting the guess wrong can cause a significant performance hit when the result has to be thrown out and the CPU waits for the results of the "right" command to be calculated. Much of the improving performance of modern CPUs is due to enhanced prediction logic, but lately the improvements have started to slow. Branch prediction accuracy has arrived at figures in excess of 98% in recent Intel architectures, and enhancing this figure can only be achieved by devoting more CPU die space to the branch predictor, a self-defeating tactic because it would make the CPU more expensive to manufacture.

Posted Date: 3/5/2013 5:42:14 AM | Location : United States







Related Discussions:- Registers - processor, Assignment Help, Ask Question on Registers - processor, Get Answer, Expert's Help, Registers - processor Discussions

Write discussion on Registers - processor
Your posts are moderated
Related Questions
Minimize the following logic function using K-maps and realize using NAND and NOR gates. F(A,B,C,D) =?_m(1,3,5,8,9,11,15) + d(2,13).

A model for parallel programming is an abstraction and is machine architecture independent. A model can be executed on several hardware and memory architectures. There are various

Q. What is the Future of Hyper threading? Current Pentium 4 based MPUs employ Hyper-threading however next-generation cores, Conroe, Merom and Woodcrest will not. As some have

Computer Organization and Architecture 1. Draw the block diagram of von Neumann Architecture and describe about its parts in brief. 2. Draw block diagram of Intel 8085 CPU o

Q. Why we need parallel programming languages? The parallel programming languages are created for parallel computer environments.  These are developed either by creating new la

Give your analysis for the following problem statement: You require to write a program that calculates the area and perimeter of a rectangle whose dimensions (Length &width) are gi

Disadvantages of Stateful Multi-Layer Inspection A firewall such as the SMLI remains completely transparent to both users and applications. Consequently, SMLI firewall does no

CSEG SEGMENT  ASSUME CS:CSEG, DS:CSEG, SS:CSEG  ORG 100h START:MOV AX, CSEG; Initialise data segment  MOV DS, AX; register using AX  MOV AL, NUM1; Take the first num

The disadvantage of specifying parameter during instantiation are: -  This has a lower precedence when compared to assigning using defparam.

Q. Example on Distribution of Data? !HPF$ PROCESSORS P1(4) !HPF$ TEMPLATE T1(18) !HPF$ DISTRIBUTE T1(BLOCK) ONTO P1  Consequently of these instructions distribution of