Register data type as sequential element, Computer Engineering

Assignment Help:

Reg data type as Sequential element

module reg_seq_example( clk, reset, d, q);

input clk, reset, d;

output q;

reg q;

wire clk, reset, d;

always @ (posedge clk or posedge reset)

if (reset) begin

q <= 1'b0;

end else begin

q <= d;

end

endmodule

There is a difference in the process of assigning to reg when modeling combinational logic: in this logic we use blocking assignments when modeling sequential logic we use nonblocking ones.

 


Related Discussions:- Register data type as sequential element

Show the mailing lists on internet, Q. Show the Mailing lists on Internet? ...

Q. Show the Mailing lists on Internet? Another exciting aspect about E-mail is that you can find groups of people who share your interests-whether you are inclined toward games

What is a resource-allocation graph, What is a resource-allocation graph? ...

What is a resource-allocation graph? Deadlocks can be described more precisely in terms of a directed graph known as a system resource allocation graph. This graph having of a

Address translation - computer architecture, Address translation: ...

Address translation: Compiler time : If it is known in advance that a program will reside at a particular location of primary memory, and then the compiler can be told to

Skip to line line number, The "SKIP TO LINE line number" is dependent on wh...

The "SKIP TO LINE line number" is dependent on which statement included in the report statement of the program. The "SKIP TO LINE line number" is dependent on "LINE-COUNT" stat

Explain about deadlock avoidance, Q. Explain about Deadlock Avoidance? ...

Q. Explain about Deadlock Avoidance? To prevent deadlocks two kinds of techniques are used: 1) Static prevention:  It employs P and V operators in addition to Semaphores to

What is fork, What is Fork Clk gets its value after 1 time unit, rese...

What is Fork Clk gets its value after 1 time unit, reset after 10 time units, enable after 5 time units, data after 3 time units. All the statements are executed in parallel.

Microprocessor, can i get the comparison of microprocessors architecture?

can i get the comparison of microprocessors architecture?

Illustrate cache dram, Q. Illustrate Cache DRAM? Cache DRAM (CDRAM) wh...

Q. Illustrate Cache DRAM? Cache DRAM (CDRAM) which is developed by Mitsubishi integrates a tiny SRAM cache (16Kb) on a generic DRAM chip. SRAM on the CDRAM can be used in two

Write Your Message!

Captcha
Free Assignment Quote

Assured A++ Grade

Get guaranteed satisfaction & time on delivery in every assignment order you paid with us! We ensure premium quality solution document along with free turntin report!

All rights reserved! Copyrights ©2019-2020 ExpertsMind IT Educational Pvt Ltd