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Reg data type as Sequential element
module reg_seq_example( clk, reset, d, q);
input clk, reset, d;
output q;
reg q;
wire clk, reset, d;
always @ (posedge clk or posedge reset)
if (reset) begin
q <= 1'b0;
end else begin
q <= d;
end
endmodule
There is a difference in the process of assigning to reg when modeling combinational logic: in this logic we use blocking assignments when modeling sequential logic we use nonblocking ones.
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The decimal equivalent of Binary number 10101 is ? Ans. 1x2 4 + 0x2 3 +1x2 2 +0x2 1 + 1x2 0 = 16 + 0 + 4 + 0 + 1 = 21.
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