Pre-processing requirements - cpld design project , Electrical Engineering

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The pre-processing unit is responsible for taking the conditioned output from the heart sensor and generating a binary count during time T1 of this waveform (datain). It will comprise a 12 bit binary counter that will be reset (active LOW) , enabled (enable active HIGH) and disabled (enable active LOW) by a control unit continually inspecting the state of the input waveform The control unit will also generate a latch pulse (active LOW) to synchronise the loading of the final count to the digital to analogue converter in the Signal Processing unit. A general system reset signal genres (active LOW) initialises the control unit to a valid starting state.

1210_Pre-processing Requirements - Cpld design project.png

The timing waveform for the control signals is shown below.

2126_Pre-processing Requirements - Cpld design project1.png


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