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Performance and Issues in Pipelining
Speedup: Firstly, we get the speedup factor that is we see how much speed up performance we get through pipelining.
First we get the ideal case for measuring the speedup.
Let n be the total number of tasks implemented through m phases of pipelines. Then m phases can process n tasks in clock cycles = m + (n-1)
Time taken to implement without pipelining = m.n
Speedup due to pipelining = m.n/[m +(n-1)].
As n>=∞ , There is speedup of n times over the non-pipelined implementation.
The commercially available 8-input multiplexer integrated circuit in the TTL family is ? Ans. In TTL, MUX integrated circuit is 74153.
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