There are 3 kinds of OCWs. The command word OCWI is utilized for masking the interrupt requests; when the mask bit corresponding to an interrupt request is value 1, then the request is blocked-up. OCWS and OCW2 are for the controlling of the mode of the 8259A and receiving EOI commands. A byte is output to OCWI using the odd address attaché with the 8259A and bytes are output to OCW2 and OCWS using the even addresses. OCW2 is differenced from OCWS by the contents of bit S of the data byte. If bit S is set value 0, the byte is put in OCW2, and if it is set value 1, it is put in OCWS. OCW2 and OCWS both are distinguished from the ICWI, which also utilized the even address, by the contents of the bit 4 of the data. If bit 4 set the value 0, then the byte is put on OCWS or OCW2 according to bit S. There is no doubt in ICW2, ICWS, ICW4, and OCWI all use the odd address because the initialization words might always follow ICWI as dictated by the initialization sequence, and an output to OCWI can't occur in the middle of this sequence.
Referring back to our discussion, bits L2-LO of OCW2 are for designating an IR level, bit 5 is used for giving EOI commands, and bits 6 and 7 are used for controlling the IR levels. Recall that when the AEOI bit in ICW4 is set to value1, the ISR bit, which is set by the interrupt request, is automatically reset at the end of the second INTA pulse, but if AEOI is equal to 0, then the ISR bit might be explicitly cleared by an EOI command, which consists of sending an OCW2 with the bit 5 that equal to value1. When an EOI command is given the meanings of the four probable combinations of bit 7, the R (rotate) bit, and bit 6, the SL (set level) bit, are:
0 0 Nonspecific, normal priority mode
0 1 specifically clears the ISR bit specify by L2-LO
1 0 Rotate priority so as to a device after being serviced has the lowest priority
1 1 Rotate priority till position specified by L2-LO is lowest
The bits in OCW2 are only provisionally reserved by the 8259A till the actions specified by them are carried out. This statement is specifically essential with regard to EOI bit. Now examine these possibilities in greater detail starting with the normal priority mode (00).
A request on IRO has the ordinarily, highest priority, 1 on the IRI has the next highest priority, and so on. When the first INTA pulse arrives the priority resolver allow only the unmasked request having the highest priority to set to its ISR bit. Because the 3 least significant bits of the ICW2, where the ICW2 specify the interrupt type and determines the interrupt pointer address, are determined by the ISR bit is set, the address of the interrupt routine depends on which of the ISR bit is set. Therefore, the interrupt routine linked with the device that linked to the highest-priority IR pin is begun first and the other requests must wait till further interrupts are allowed.
Under the normal priority mode, if the ISRn is set then the priority resolver will be not distinguish any requests on IR7 through IR(n+l), but will distinguish unmasked requests on IR(n -1) through IRO, therefore if the IF flag in the CPU has been reset to value 1, requests having higher priority than the one being processed might be cause the current interrupt routine to be interrupted whereas those having lower priorities are kept waiting. The lower-priority requests are processed according to their priorities as the higher-priority ISR bits are cleared. If AEOI is equal to1, the ISR bit corresponding to an interrupt is automatically cleared at the end of the second INTA pulse. When AEOI is equal to 0 the ISR might be cleared by the interrupt routine by setting bit 5 of OCW2.