Memory address decoding-microprocessor, Assembly Language

Memory Address Decoding

Binary Decoders - Decoders have 2n-inputs and n outputs, each input combination results in a single output line contain a 1, and all other lines contain a 0 on the output. Examples of use are decoding memory addresses and CPU instructions.Typically Decoders have an enable when 1 enables decoding the input to 1 on a single output, when not enabled all outputs are zero. The switching function for an enabled 2-input binary decoder is:

1802_switching func1.jpg

The 2 to 4 decoder representation is:

238_2-4 decoder.jpg

1637_2 inputs.jpg

Memory Address Decoding - Figure indicate a 16K by 1 bit word memory (8 bit words are implemented by selecting 8 bits as a group, for instance). Since 214 is about 16K, a single decoder would require 14 inputs and 214 output

196_ram modules.jpg

359_decoder.jpg

The memory decoder is linked to the CPU by the address bus. Each memory cell is linked to an output and input data bus, a write/read control, and the decoder which enables the memory cell when the suitable address appears. The decoder ensures that just a single memory cell is activated at a time for either output or input.

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