Interrupt priority management-microprocessor, Assembly Language

Interrupt Priority Management

The interrupt priority management logic indicated in given figure can be implemented in several ways. It does not required to be present in systems which utilized software priority management  or simple daisy chaining, but more complicated systems might be require  the efficiency  gained  by including  hardware  for managing  the I/O interrupts. Several manufacturers have made priority management devices available along with INTEL. Although such type device  made  by 1 manufacturer could  be utilize with  processors  made  by  other manufacturers, mostly there are fewer compatibility problems if the CPU and interrupt priority device are produced by the similar company. Therefore, we will be concerned with the Intel 8259A programmable interrupt controller (PIC), which has been particularly designed to work with the 8088/8086 as well as other members of the Intel microprocessor family.

The 8259A has been designed so that it may operate alone or in concert with other 8259As. In order to restrict the starting discussion, an interrupt system involving  a single 8259A device is considered  first; then the discussion is extended to systems that may include as many as nine 8259As.

 

Posted Date: 10/10/2012 8:22:22 AM | Location : United States







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