Instruction pipelines, Computer Engineering

Instruction Pipelines

As discussed previous, the stream of instructions in the instruction implementation cycle, can be realized through a pipeline where overlapped implementation of different operations are performed. The process of implenting the instruction involves the following main steps:

  • Fetch the instruction by the main memory
  • Decode the instruction
  • Fetch the operand
  • Implement the decoded instruction

These four steps become the candidates for phases for the pipeline, which we state as instruction pipeline (It is given in Figure).

                                                471_Instruction Pipelines.png

                                                          Figure: Instruction Pipeline

While, in the pipelined implementation, there is overlapped implementation of operations, the four phases of the instruction pipeline will work in the overlapped manner. Firstly, the instruction address is fetched from the memory to the first phase of the pipeline. The first phase fetches the instruction and provides its output to the second phase. Whereas, the second phase of the pipeline is decoding the instruction, the first phase gets another input and provides the next instruction. When the first instructions have been decoded in the second phase, then its output is fed to the third phase. When the third phase is fetching the operand for the first instruction, then the second phase gets the second instruction and the first phase gets input for another instruction and so on. In this manner, the pipeline is implementing the instruction in an overlapped way increasing the speed of execution and throughput.

The situation of these overlapped operations in the instruction pipeline can be demonstrated through the space-time diagram. In Figure, firstly we show the space-time diagram for non-overlapped implementation in a sequential environment and then for the overlapped pipelined environment. It is clear from the two diagrams that in non-overlapped implementation, results are achieved only after 4 cycles while in overlapped pipelined implementation, after 4 cycles, we are receiving output after every cycle. Soon in the instruction pipeline, the instruction cycle has been deduced to ¼ of the sequential implementation.

                                      879_Space-time diagram for Non-pipelined Processor.png

                                                Space-time diagram for Non-pipelined Processor

                                    967_Space-time diagram for Overlapped Instruction pipelined Processor.png

                                              Space-time diagram for Overlapped Instruction pipelined Processor

Posted Date: 3/2/2013 7:06:09 AM | Location : United States

Related Discussions:- Instruction pipelines, Assignment Help, Ask Question on Instruction pipelines, Get Answer, Expert's Help, Instruction pipelines Discussions

Write discussion on Instruction pipelines
Your posts are moderated
Related Questions
Explain Excess 3 Codes Ans. Excess 3 Codes 1. This is the other form of BCD code. All decimal digits are coded in 4 bit binary code. 2. The code for all decimal di

Please explain the construction and working of calomel electrode..

Q. How can one decide this decimal position? Decimal position can be signified by a position between flip-flops (storage cells in computer). However how can one decide this dec

What is meant by concurrent execution of database transactions in a multi user system

Which objects are independent transport objects? Domains, Data elements, Tables, Technical settings for tables, Secondary indexes for transparent tables, Structures, Views, Ma

Define the Fundamentals of computer system A computer processes digital information. In order to do that it runs (executes) a machine language program. As an illustration, when

Get a listing of the name, commission rate, and hire date of all salesmembers who sell to commercial customers. Sort the result in order from the 1st hired to the most recently hir

How can we pass selection and parameter data to a report? There are three options for passing selection and parameter data to the report. Using SUBMIT...WITH Using a rep

Handshake control of data transfer during an input operation:   . Handshake control of data transfer during an output operation o   Interface to CPU and Memory o

Determine the advantages of BCD Adder Now let us see the arithmetic addition of two decimal digits in the BCD, with a possible carry from previous stage. As each input digit do