General Bus Operation
The 8086 has a joined data and address bus commonly referred to as a time multiplexed address and data bus. The major reason behind multiplexing address and data over the similar pins is the maximum utilization of processor pins and it facilitates the use of 40 pin standard DIP package. The bus may be de-multiplexed by using a few transceivers and latches, whenever required. In the following text, a general bus operation cycle is described.
Mainly all the processor bus cycles contain of at least 4 clock cycles. These are referred to as T4, T3, T2 and T1• the address is transmitted by the processor during T1. It is present on the bus just for 1 cycle. During T2, for example- in the next cycle, the bus is tristated for altering the direction of bus for the following data read cycle. The data transfer takes place during T4and T3. In case, an addressed device is slow and shows
'NOT READY' status the wait states Tware inserted between T3 and T4. During wait periodthese all clock states are known wait states (Tw),idle states (Ti), or inactive states. The processor utilize these cycles for internal housekeeping. The address latch enable (ALE) signal is emitted during T, by the bus controller (maximum mode) orthe processor (minimum mode) depending upon the status of the MN/MX input. The negative edge of this ALE pulse is utilized to separate the address and the status or data information. In maximum mode, the status lines S0, S1 and S2 are utilize to indicate the type of operation as described in the pin description of this unit. Status bits BHE/s7 are multiplexed with BHE and signalhigher order address bits. Address is valid during T1 while the status bits S3 to S7 are valid during T2 through T4. The Figure2.7 shows a general bus operation cycle of 8086.