Flag manipulation and processor control instructions , Assembly Language

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Flag Manipulation and Processor Control Instructions

These instructions control the functioning of available hardware inside the processor chip. These are categorized into these types; (a) machine control instructions and (b) flag manipulation instructions. The flag manipulation instructions are directly modify some of the flags of 8086. The machine control instructions can control the usage and execution of the bus. The flag manipulation instructions and their functions are following:

CLC -   Clear carry flag

CMC -   Complement carry flag

STC -   Set carry flag

CLD -   Clear direction flag STD:-Set direction flag CLI - Clear interrupt flag STI - Set interrupt flag

These instructions modify directly the direction (DF), carry (CF) and interrupt (IF) flags. The DF and IF flag, which can be modified by using the flag manipulation instructions, further control the processor operation; like the auto increment or auto decrement and the interrupt responses modes. Thus the respective instructions may also be called as processor or machine control instructions. The other flags may be modified by using POPF  and SAHF instructions, which are termed as the data transfer instructions. No direct instructions are available for modifying the status flags except the carry flag.

The machine control instructions supported by the 8086 and 8088 are listed along with their functions below. These machine control instructions do not need any operand.

 

WAIT   -   Wait for Test input pin to go low

HLT      -   Halt the processor

NOP     -   No operation

ESC      -   Escape to external device like NDP (numeric co-processor)

LOCK   -   Bus lock instruction prefix.

After execution of the HLT instruction, the processor goes to the halt state, as explained in first Chapter. The two ways to pull it out of the halt state are to reset processor or interrupt it. When instruction NOP is executed, the processor does not execute any operation until the 4 clock cycles, except incrementing the IP by one. Then it continues with further execution after the 4 clock cycles. When executed ESC instruction, frees the bus for an external master like a peripheral or coprocessor devices.  The LOCK prefix may seem with another instruction.  When it is executed, the bus access is not endorsed for another master until the lock prefixed   instruction is executed fully. This instruction is utilized in the case of programming for multiprocessor systems. The instruction WAIT when executed holds the operation of processor with the current status until the logic level on the TEST pin set low. The processor goes on inserting WAIT states in the instruction cycle, until the TEST pin set low. Once the TEST pin set low, it continues with further execution.

 


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