External Hardware-Interrupts

External hardware-interrupts are generated by controllers of external devices or coprocessors and are connected to the processor pin for Non Mask able Interrupts (NMI) or to the pin for Mask able Interrupts (INTR). The NMI line is generally booked for interrupts that occur because of fatal errors like a power distortion or parity error.

Interrupts from external devices may also be associated to the processor via the Intel 8259A Programmable Interrupt Controller (PIC). The CPU utilizes a group of I/O ports to control the PIC and the PIC puts its signals on the INTR pin. The PIC makes possible to enable or disable interrupts and to change the priority levels under supervision of a program.

The instructions CLI and STI may be utilized to enable/disable interrupts on the INTR pin, it has not any effect on NMI interrupts.

 

Posted Date: 10/10/2012 8:13:42 AM | Location : United States

Ask an Expert

Related Discussions:- External hardware-interrupts-microprocessor, Assignment Help, Ask Question on External hardware-interrupts-microprocessor, Get Answer, Expert's Help, External hardware-interrupts-microprocessor Discussions

Write discussion on External hardware-interrupts-microprocessor
Your posts are moderated

Write your message here..

Related Questions

Pin functions of 8086-microprocessor, Pin functions for the minimum mode o... Pin functions for the minimum mode operation of 8086 are following: 1) M/I/O -Memory/IO: This is a status line logically equivalent to S2 in maximum mode. When it is low, it

Inc-arithmetic instruction-microprocessor, INC: Increment : - This instruct... INC: Increment : - This instruction increments the contents of the particular memory or register location by the value 1. All the condition code flags are affected except the carry

8251 programmable/communication interface-microprocessor, 8251 Programmable... 8251 Programmable/Communication Interface As an instance of a serial interface device let us suppose Intel's 8251 A programmable communication interfaces. The 8251A is diagram

Introduction to evaluation, This unit introduces the topic of evaluating in... This unit introduces the topic of evaluating interactive products. It is a short unit as evaluation is discussed in more detail in Block 4. Its brevity should give you additional t

Mmm development board, Write an account of your findings and produce a repo... Write an account of your findings and produce a report containing all aspects of the above. Include a step-by-step 'simple User Guide' so that your program can be operated as inten

Program, wap proram for bthe addition of two 3*3 matrix wap proram for bthe addition of two 3*3 matrix

Cache memory-microprocessor, Cache Memory Caching is a technology based... Cache Memory Caching is a technology based on the memory subsystem of any computer. The majoraim of a cache is to accelerate the computer while keeping the cost of the computer

Flowchart, ALP to preform of two 16-bit numbers in register addressing mode... ALP to preform of two 16-bit numbers in register addressing mode

Assembly language, program to add two matrices program to add two matrices

Programs solution, chp 3 of assemly chp 3 of assemly