External hardware-interrupts are generated by controllers of external devices or coprocessors and are connected to the processor pin for Non Mask able Interrupts (NMI) or to the pin for Mask able Interrupts (INTR). The NMI line is generally booked for interrupts that occur because of fatal errors like a power distortion or parity error.
Interrupts from external devices may also be associated to the processor via the Intel 8259A Programmable Interrupt Controller (PIC). The CPU utilizes a group of I/O ports to control the PIC and the PIC puts its signals on the INTR pin. The PIC makes possible to enable or disable interrupts and to change the priority levels under supervision of a program.
The instructions CLI and STI may be utilized to enable/disable interrupts on the INTR pin, it has not any effect on NMI interrupts.