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Q. Explain SR Latch using NOR gates?
Let's inspect the latch more closely.
i. Suppose initially 1 is applied to S leaving R to 0 at this instance. The instant S=1 output of NOR gate 'b' alters to 0 which implies that Q becomes 0 and almost instantly Q becomes 1 as both inputs (Q and R) to NOR gate 'a' become 0. Change in the value of S back to 0 doesn't change Q as input to NOR gate 'b' now are Q = 1 and S=0. So flip-flop stays in set state even after S returns to 0.
ii. If R goes to 1 then latch obtains clear state. On changing R to 1, Q alters to 0 irrespective of state of flip-flop and as Q is 0 and S is 0 then Q¯ becomes 1. Even after R returns to 0 Q remains 0 it implies that latch is in clear state.
iii. When both S & R go to 1 concurrently two outputs go to 0. This gives undefined state.
The NOR gate. The NOR gate is equivalent to an OR gate followed by a NOT gate so that the output is at logic level 0 when any of the inputs are high otherwise it is at logic le
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