Explain asynchronous decade counter, Computer Engineering

Draw the circuit diagram of Asynchronous decade counter and explain its working.

Ans:

To  design  a  circuit diagram of decade  asynchronous  counter  initially  we  draw  the  circuit  for  MOD  16 asynchronous counter that counts from 0 to 15 by using four flip-flop (JK or T flipflop). This must count from 0 to 9 and then come to 0. The initial state to be skipped is 1010 (10) here Q3 and Q1 are 1 and Q2 and Q0 are 0 if we obtain Q3 and Q1 and applied these to a NAND gate after that the output of the NAND gate will be low only where Q3 and Q1 are high. Such signal can be utilized to asynchronously clear all flipflops to make the counting state 0000. In this method MOD 16 counter will be limited to count 10 states i.e. from 0 to 9.

702_Explain Asynchronous decade counter.png

The circuit diagram of Asynchronous decade counter

Posted Date: 5/4/2013 6:39:58 AM | Location : United States







Related Discussions:- Explain asynchronous decade counter, Assignment Help, Ask Question on Explain asynchronous decade counter, Get Answer, Expert's Help, Explain asynchronous decade counter Discussions

Write discussion on Explain asynchronous decade counter
Your posts are moderated
Related Questions
An operating system contains 3 resource classes. The number of resource units in these classes is 7, 7 and 10. The current resource allocation state is shown below:

Syntax and Semanticsx and Semantics for First-order logic - artificial intelligence: Propositional logic is limited  in its expressiveness: it may just represent true and false

a) Total available bandwidth = 1 Mbps = 1000 Kbps Each user requires send data at the rate of = 500 kbps As it is circuit switched network we have to dedicate the bandwidth So the

what is homogeneous coordinate system

What is a Region? A Region is a continuous area of a process's address space (like text, data and stack). The kernel in a "Region Table" that is local to the process mainta

What are different types of Log records? V1 and V2.  V1 must be processed before V2.  But, we can have more than single V2 logs

Q. Show Error detection mechanism? Error detection mechanism can be described as below: Figure: Error detection and correction

Draw a circuit of an NMOS inverter and explain its operation

The most important in the project are to develop application: 1- Web Conference this will help both the jobseeker and employer to meet through web conference and follow the proc

Q. Program size for different Instruction Set Approaches? Assumptions: Complex Instruction is: Add C, A, B having 16 bit addresses and 8 bit data operands All opera