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In this technique, operand field of instruction includes an address and an index register thatcomprises an offset. This addressing scheme is normally used to address the consecutive locations of memory (that may store the elements of an array). Index register is a special CPU register which contains an index value. Contents of the operand field A are taken to be address of the initial or reference location (or first element of array). The index register specifies distance between the starting address and address of that operand.
For illustration: to address of an element B[i] of an array B, B,....B[n] with every element of array stored in two consecutive locations and starting address of array is presumed to be 101, the operand field A in instruction shall comprises the number 101 and index register R will contain the value of expression (i - 1) × 2.
So for first element of the array index register will hold 0. For addressing 5th element of the array A=101 while index register will hold:
(5- 1) × 2 = 8
So address of 5th element of array B is=101+8=109. In B but the element will be stored in location 109 and 110. To address any other element of array changing the content of index register will serve.
So the effective address in this technique is calculated as:
EA = A +(R)
D = (EA)
(DA is Direct address)
As the index register is employed for iterative applications so the value of index register is decremented or incremented after each reference to it. In numerous systems this operation is performed automatically at the time of the course of an instruction cycle. This feature is termed as auto-indexing. Auto indexing can be auto-decrementing or auto-incrementing. The choice of register to be employed as an index register varies from machine to machine. Some machines use general-purpose registers for this purpose whereas other machines can specify special purpose registers referred to as index registers.
Figure: For Displacement Addressing
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