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Let's design a synchronous BCD counter. A BCD counter follows a sequence of ten states and returns to 0 after count of 9. These counters are also known as decade counters. This type of counter is useful in display applications in which BCD is essential for conversion to a decimal readout. Figure demonstrates characteristic table for this counter.
Figure: Characteristic table for decade counter
There are 4 flip-flop inputs for Decade counter it implies A, B, C, D. The subsequent state of flip-flop is given in table. JA and KA denotes flip flop input corresponding to flip-flop-A. Please note this counter need 4-flip-flops.
From this flip flop input equations are simplified by K-Maps as displayed in figure below. Unused minterms from 1010 through 1111 are considered as don't care conditions.
Figure: K-maps for Decade counter
So simplified input equation for BCD counter are as below:
Logic circuit can be designed with 4 JK flip flops and 3 AND gates.
Figure: Logic Diagram for decade counter.
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