Design a mod-5 synchronous counter using J-Kflip-flops, Computer Engineering

What are synchronous counters? Design a Mod-5 synchronous counter using J-K Flip-Flops.

Ans.

Synchronous Counters: It means that all flip-flops are clocked concurrently. The clock pulses drive the clock input of each flip-flop together hence there is no propagation delay.

Mod-5 Counter Synchronous Counter: This have five counter states. The counter design table for such counter shows the three flip-flop and their states also (0 to 5 states), as in table (a), the 6 inputs needed for the three flip-flops. The flip-flop inputs needed to step up the counter from the current to the next state have been worked out along with the assist of the excitation table illustrated in the table.

 

Input

 

pulse

 

 

Count

Counter States

 

 

A          B          C

Flip-Flop Inputs

 

JA                  KA

 

JB                KB                                        JC                  KC

0

0           0          0

1             X

0             X                            0              X

1

1           0          0

X             1

1             X                            0              X

2

0           1          0

1             X

X            0                           0              X

3

1           1          0

X             1

X            1                           1              X

4

0           0          1

0             X

0             X                           X             1

5(0)

0           0          0

 

 

                                                             Table (a) counter Design Table for Mod-5 Counter

A flip-flop:  The first state is 0. This change to 1 after the clock pulses. Thus JA must be 1 and KA may be 0 or 1 (i.e. X ).

B flip-flop: The first state is 0 and this keeps unchanged after the clock pulse. Thus JB must be 0 and KB may be 0 or 1 (i.e. X)

C flip-flop: The state keeps unchanged. Thus Jc must be 0 and KC must be X. The flip-flop input values are entered in Karnaugh maps demonstrated in Table (b) [(i) (ii) (iii) (iv) (v) and (vi)] and a boolean expression is determined for the inputs to the 3-flip-flops and after that each expression is simplified. All the counter states have not been utilized; X's (don't) are entered to indicate un-utilized states. For each input the simplified expressions demonstrated under each map. At last, these minimal expressions for the flip-flop inputs are utilized to illustrate a logic diagram for the counter that is demonstrated in fig. (b).

664_Karnaugh Maps for MOD-5 Synchronous Counter.png

Table (b) Karnaugh Maps for MOD-5 Synchronous Counter

766_Logic Diagram of MOD-5 Synchronous Counter.png


Fig. (b) Logic Diagram of MOD-5 Synchronous Counter

Posted Date: 5/2/2013 8:45:33 AM | Location : United States







Related Discussions:- Design a mod-5 synchronous counter using J-Kflip-flops, Assignment Help, Ask Question on Design a mod-5 synchronous counter using J-Kflip-flops, Get Answer, Expert's Help, Design a mod-5 synchronous counter using J-Kflip-flops Discussions

Write discussion on Design a mod-5 synchronous counter using J-Kflip-flops
Your posts are moderated
Related Questions
Which approaches do not require knowledge of the system state? Ans. Deadlock detection, deadlock prevention and deadlock avoidance; none of the given require knowledge of the s

Process of Breadth first search: It's very useful to think of this search as the evolution of the given tree, and how each string of letters of word is found via the search in

Specifying Constraint Problems: However as with most successful "AI" techniques there constraint solving is all about solving problems as: somehow phrase the intelligent task

Explanation The values of global variables can be used and changed all over the project within all scripts and libraries. However it is highly recommended to remain the number o

Which one is an error reporting protocol? An error reporting protocol is ICMP.

We have multiple instances in RTL (Register Transfer Language), do you do anything special during synthesis stage? Whereas writing RTL(Register Transfer language),say in Verilo

The most common type of non-volatile memory is the ROM device. This device is read only and the data is masked into the chip during manufacture. Variations of the ROM are one off p

How to configure TSM server

Integrating Virtual Memory, TLBs, and Caches - computer architecture:   There are 3 types of misses: 1. a cache miss 2. TLB miss 3. a page fault 2 techniqu

Q. Write a program to perform multiplication of two numbers in specified radix. Check that entered numbers are in specified radix or not else error message should be displayed.