What are synchronous counters? Design a Mod5 synchronous counter using JK FlipFlops.
Ans.
Synchronous Counters: It means that all flipflops are clocked concurrently. The clock pulses drive the clock input of each flipflop together hence there is no propagation delay.
Mod5 Counter Synchronous Counter: This have five counter states. The counter design table for such counter shows the three flipflop and their states also (0 to 5 states), as in table (a), the 6 inputs needed for the three flipflops. The flipflop inputs needed to step up the counter from the current to the next state have been worked out along with the assist of the excitation table illustrated in the table.
Input
pulse
Count

Counter States
A B C

FlipFlop Inputs

JA KA

JB KB JC KC

0

0 0 0

1 X

0 X 0 X

1

1 0 0

X 1

1 X 0 X

2

0 1 0

1 X

X 0 0 X

3

1 1 0

X 1

X 1 1 X

4

0 0 1

0 X

0 X X 1

5(0)

0 0 0



Table (a) counter Design Table for Mod5 Counter
A flipflop: The first state is 0. This change to 1 after the clock pulses. Thus JA must be 1 and KA may be 0 or 1 (i.e. X ).
B flipflop: The first state is 0 and this keeps unchanged after the clock pulse. Thus JB must be 0 and KB may be 0 or 1 (i.e. X)
C flipflop: The state keeps unchanged. Thus Jc must be 0 and KC must be X. The flipflop input values are entered in Karnaugh maps demonstrated in Table (b) [(i) (ii) (iii) (iv) (v) and (vi)] and a boolean expression is determined for the inputs to the 3flipflops and after that each expression is simplified. All the counter states have not been utilized; X's (don't) are entered to indicate unutilized states. For each input the simplified expressions demonstrated under each map. At last, these minimal expressions for the flipflop inputs are utilized to illustrate a logic diagram for the counter that is demonstrated in fig. (b).
Table (b) Karnaugh Maps for MOD5 Synchronous Counter
Fig. (b) Logic Diagram of MOD5 Synchronous Counter