Design a mod-12 synchronous up counter, Computer Engineering

Design a mod-12 Synchronous up counter.

Ans. Design of a mod 12 synchronous counter by using D-flipflops.

I state table
Present state Next state Required D Inputs

A	B	C	D	A	B	C	D	DA	DB	DC	DD
0	0	0	0	0	0	0	1	0	0	0	1
0	0	0	1	0	0	1	0	0	0	1	0
0	0	1	0	0	0	1	1	0	0	1	1
0	0	1	1	0	1	0	0	0	1	0	0
0	1	0	0	0	1	0	1	0	1	0	1
0	1	0	1	0	1	1	0	0	1	1	0
0	1	1	0	0	1	1	1	0	1	1	1
0	1	1	1	1	0	0	0	1	0	0	0
1	0	0	0	1	0	0	1	1	0	0	1
1	0	0	1	1	0	1	0	1	0	1	0
1	0	1	0	1	0	1	1	1	0	1	1
1	0	1	1	0	1	0	0	0	1	0	0

Firstly draw the state table containing present state, subsequent state and required flip-flop input to provide the transition. D flip flop offers the output similar as the next state itself. After that, solve through using K maps to determine DA DB DC DD for all states.
Unutilized states are 1100,1101,1110,1111 they can be function as don't care conditions from the table. Depict Karnaugh-maps for DA, DB, DC and DD as follows and acquire Boolean expressions for them.

355_Design a mod-12 Synchronous up counter.png

569_Design a mod-12 Synchronous up counter12.png

2281_Design a mod-12 Synchronous up counter21.png

Related Discussions:- Design a mod-12 synchronous up counter

Paging, specification of paging ram size is 12 frames

specification of paging ram size is 12 frames

Mips - computer architecture, MIPS - computer architecture: The MIPS ...

MIPS - computer architecture: The MIPS ISA, so far 3 instruction formats Fixed 32-bit instruction 3-operand, load-store architecture 32 general-purpose register

Towers of hanoi problem, The Towers of Hanoi Problem Towers of Hanoi pro...

The Towers of Hanoi Problem Towers of Hanoi problem is described. There are three pegs on which disks are "threaded" (there are holes in the disks to allow them to be placed on

How to maintain lists, How to maintain lists? To return from a high li...

How to maintain lists? To return from a high list level to the next-lower level (SY-LSIND), the user chooses back on a secondary list. The system then gives the currently dis

Define superscalar processors, In scalar processors just one instruction is...

In scalar processors just one instruction is implemented per cycle which means just one instruction is issued for each cycle and only that one instruction is completed however the

Returns and procedures definitions in 8086, Q. Returns and Procedures defin...

Q. Returns and Procedures definitions in 8086? 8086 microprocessor supports RET and CALL instructions for procedure call. CALL instruction not only branches to indicate address

What is the sequence in which resources may be utilized, What is the sequen...

What is the sequence in which resources may be utilized? Under normal mode of operation, a process might be utilize a resource in the following sequence: • Request: If the

Recent parallel programming models, A model for parallel programming is an ...

A model for parallel programming is an abstraction in addition its machine architecture is independent. A model is able to be implemented on different hardware and memory architect

Show the example of internet address, Q. Show the example of internet addre...

Q. Show the example of internet address? The following can be a typical person understandable address on Internet: VVS @ expertsmind.us VVS is an username which in gene

QUELING SYTEM , SHOW THAT AVERAGE NUMBER OF UNIT IN A (M/M/1) QUELING SYTEM...

SHOW THAT AVERAGE NUMBER OF UNIT IN A (M/M/1) QUELING SYTEM IS EQUAL TO P/(1-p). NOTE:P=ROW

Write Your Message!

Name

Email id

Message

Verfication Code

User Account

All Pages