D Flip Flop

As we have seen  in the SR flip flop  when the inputs  S= R  are applied the forbidden or indeterminate state occurs.  This state can destabilize the SR file flop. It can be avoided by D flip flop. The  D flip flop can be constructed using SR flip flop. The  D flip flop  has one  inputs  D and a clock  inputs.  The logic diagram of D flip  flop  is shown in figure.

The  D input is directly  connected to the S input  and its  complement is connected to R input. since  the output  is delayed because the output  does  not change  immediately when the clock  pulse goes  from 0 to 1  the inputs  is thus delayed by a clock  pulse  before  appearing  at the output. So  it is also  known  as delay flip  flop.

 

Posted Date: 4/4/2013 12:58:27 AM | Location : United States

Ask an Expert

Related Discussions:- D flip flop - introduction to microprocessors, Assignment Help, Ask Question on D flip flop - introduction to microprocessors, Get Answer, Expert's Help, D flip flop - introduction to microprocessors Discussions

Write discussion on D flip flop - introduction to microprocessors
Your posts are moderated

Write your message here..

Related Questions

Society in engineering, Cite a specific example in which the engineer must ... Cite a specific example in which the engineer must provide maximum efficiency for a given cost

Tri state devices, Tri State Devices Tri  State  devices have three  st... Tri State Devices Tri  State  devices have three  states logic 1  logic  0 and high  impedance. A tri state device ( Buffer/ Inverter) has three  lines output  enable as shown

Explain immediate data addressing mode, Explain immediate data addressing m... Explain immediate data addressing mode (with examples) available in microprocessors. Immediate Mode: The operand given in immediate mode is the actual data itself.

Find the ratio of the speed of the generator, Q. A dc shunt machine has an ... Q. A dc shunt machine has an armature winding resistance of 0.12  and a shunt-?eld winding resistance of 50 . The machine may be run on 250-V mains as either a generator or a mot

Effect of power factor correction capacitors, For a 50kW three phase rectif... For a 50kW three phase rectifier connected at 415 V to a point of common coupling with a short circuit capacity 500kVA modelled as an inductive source, design filters to make the s

Apply required morphological operations and give the output, You are given ... You are given a binary image consisting of only zeros and ones, see image-A. Apply required morphological operations and give the output images on the grid.

Find current in bjt, Q. A BJT is biased by the method shown in Figure. If V... Q. A BJT is biased by the method shown in Figure. If V BEQ = 0.7V, β = 100, V CEQ = 10 V, and I CQ = 5 mA, find I 1 , I 2 , and IEQ.

Not gate- introduction microprocessors , Normal 0 false fals... Normal 0 false false false EN-IN X-NONE X-NONE

Find the value of noncoherent source, If E b /N 0 = 20 in a coherent ASK s... If E b /N 0 = 20 in a coherent ASK system, find the value of Eb/N0 that is needed in a noncoherent ASK system to yield the same value of Pe as the coherent system.

Define time constant, Time constant Time constant, defines as time for ... Time constant Time constant, defines as time for current achieve maximum (IM) if this maintain the early promotion rate current.