CONSTANTS, Assembly Language

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Logical instruction-microprocessor, Logical Instruction : This type of...

Logical Instruction : This type of instructions is utilized for carrying out the bit by bit shift, basic logical operations or rotate. All of the condition code flags are affe

Cache components-microprocessor, Cache components The cache sub-system ...

Cache components The cache sub-system may be divided into 3 functional blocks: Tag RAM, SRAM and theCache Controller. In real designs, these blocks can be implemented  by multi

Test-logical instruction-microprocessor, TEST : Logical Compare Instructio...

TEST : Logical Compare Instruction: The TEST instruction performs bit by bit logical AND operation on the 2 operands. Each bit of the result is then set to value I, if the equival

Login system, a pseudo-code to add username and password combination up to ...

a pseudo-code to add username and password combination up to a limit of 10

Cbw-cwd-arithmetic instruction-microprocessor, CBW: Convert Signed Byte to...

CBW: Convert Signed Byte to Word: This instruction converts a signed byte to a signed word. In other terms, it copies the sign bit of a byte to be converted to all of the bits in

Cmp-arithmetic instruction-microprocessor, CMP: Compare: - This instructio...

CMP: Compare: - This instruction compares the source operand, which can be a register or memory location an immediate data with a destination operand that might be a register or a

The real time system (rts)-microprocessor, The real time System (RTS) : ...

The real time System (RTS) : Calling the clock real-time is somewhat of a misnomer because it only shows the time setting it has been given. The RTC is the other half of chip

4 bit 2s complement multiplier, How to design 4 bit signed 2s complement m...

How to design 4 bit signed 2s complement multiplier?

8086 program, program to arrange a given set of numbers in descending order...

program to arrange a given set of numbers in descending order

Hold response sequence-microprocesssor, Hold Response Sequence The HOLD...

Hold Response Sequence The HOLD pin is examined at leading edge of each clock pulse. If it is received active line by the processor before T4 of the earlier cycle/during the T1

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