Clocked sr flip flop, Computer Engineering

Clocked SR flip flop

1759_Clocked SR Flip Flop1.png

2075_Clocked SR Flip Flop.png

A clock pulse is a sequence of logic 0, logic 1, and logic 0 occuring on the CLK input. Time tn occurs before the clock pulse and

time tn+1 occurs after the clock pulse.

 

 

t

t

 

S

R

Q

Q'

 

Q

Q'

 

 

 

 

 

 

 

 

0

0

0

1

0

1

} No change

0

0

1

0

1

0

0

1

0

1

0

1

} Reset

0

1

1

0

0

1

1

0

0

1

1

0

} Set

1

0

1

0

1

0

1

1

0

1

?

?

} Operation Indeterminate

1

1

1

0

?

?

Posted Date: 8/27/2012 1:50:24 AM | Location : United States







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