Reference no: EM131322903

In this problem you will design a digital stopwatch with the following characteristics: Its display will consist of two two-digit decimal numbers representing minutes and seconds. The smallest display will be OO:OO, the largest 5959. The decimal digits will be seven-segment displays. The user will have three buttons available: a RESET button, which causes the time display to return to 0O:OO; a STOP button, which causes the stopwatch to freeze if it is running; and a GO button, which causes the stopwatch to start running if it is frozen. Pushing RESET while the stopwatch is running should set the time to 0O:00 but not freeze it. In addition to the seven-segment display module discussed previously, you have available modulo-6 and modulo-l0 counters. In your design you should use the following symbols:

A modulo-N counter is a sequential circuit having N states corresponding to the binary numbers 0 through N - 1. When enabled, the counter sequences from one state to the next on every clock pulse; thus the outputs of an enabled modulo-6 counter cycle through the sequence 000, 001, 010, 011, 100, 101, 000, .... Section 5.1.5 contains some comments on the implementation of counters. The counter modules you are to use in this problem have outputs for the current counter state (numbered from most to least significant bit, bit 0 being the least significant) and several other terminals, The line labeled C is the clock input to the counter (you may assume that it is positive edge-triggered). R is a reset input, which, if 1, will force the counter state to 0 at the next clock pulse. E: is the enable input; counting will be inhibited if E is 0. Finally, OV is an overflow output, which is 1 only when E is 1 and the counter state is at the maximum (N - 1). In other words, OV is 1 if the next clock pulse would take the counter from state N - 1 to state 0. Note: Do not assume that Or/ is hazard-free; it may glitch momentarily after clock transitions.

A. Draw a circuit diagram for the digital stopwatch, You may use the modules discussed above and any other modules discussed in section 5.1. Your circuit will have a clock input with pulses supplied at l-S intervals and RESET, STOP, and GO inputs that are 1 whenever the corresponding buttons are pressed. You may assume that each button remains pressed long enough to overlap at least one clock pulse; hence you need not worry about latching these inputs. Try to use as many building-block modules as possible and a minimum of ad hoc gate circuitry. One solution uses four seven-segment displays, two modulo-l0 counters, two modulo-6 counters, one edge-triggered D flip-flop, one two-input multiplexer, and one inverter. Give a short verbal description of how your circuit works, along with the circuit itself.

B. Are there any circumstances under which your stopwatch could function incorrectly because of metastable states? If so, describe them. How likely would these be to cause incorrect operation in practice? Explain your reasoning.