Compute the delay through each logic network

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Use logical effort to compute the delay through each logic network of Question Q4-3. Assume all transistors are of minimum size and each output drives a minimum-size inverter and P=1.

Question4-3

For each of these logic networks, draw the logic diagram and find the critical path, assuming that the delay through all two-input gates is 2 and the delay through an inverter is 1.

a) NAND2(NAND2(a,b),NOT(c)).

b) NAND2(NAND2(a,NOT(b)),NAND2(c,d)).

c) NAND2(NAND2(a,b),NAND2(c,d))

Reference no: EM131412041

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