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Q1) Suppose a computer's address size is K bits (using byte addressing), the cache size is k bits (using byte addressing), the cache size is S bytes, the block size is B bytes, and the cache is A -way set associative. Assume that B is a power of two, so B = 2b. Figure out what the following quantities are in terms of S, B, A, b and K:
(a) the number of sets in the cache;
(b) the number of index bits in the address;
(c) the number of total bits needed to implement the cache
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